76 research outputs found
Model Driven Engineering Benefits for High Level Synthesis
This report presents the benefits of using the Model Driven Engineering (MDE) methodology to solve major difficulties encountered by usual high level synthesis (HLS) flows. These advantages are highlighted in a design space exploration environment we propose. MDE is the skeleton of our HLS flow dedicated to intensive signal processing to demonstrate the expected benefits of these software technologies extended to hardware design. Both users and designers of the design flow benefit from the MDE methodology, participating to a concrete and effective advancement in the high level synthesis research domain. The flow is automatized from UML specifications to VHDL code generation and has been successfully evaluated for the conception of a video processing application
FPGA Configuration of Intensive Multimedia Processing Tasks Modeled in UML
Recent research have demonstrate interests in a codesign framework    that allows description refinement at different abstraction level.    We have proposed such a framework that allows SoC resources    allocation for regular and repetitive tasks found in intensive    multimedia applications. Nevertheless, the framework does not directly target    reconfigurable architectures, the difficult job of placing and    routing an application on a FPGA being postponed to a dedicated    tool. In order to limit the number of synthesis on this external    tool, we propose an algorithm that, from a high level description    of an intensive multimedia application, estimates the resource    usages on a given FPGA architecture. This algorithm makes use of a    simple mathematical formalism issued from case study    implementations
Complementary Communication Path for Energy Efficient On-Chip Optical Interconnects
International audienceOptical interconnects are considered to be one of the key solutions for future generation on-chip interconnects. However, energy efficiency is mainly limited by the losses incurred by the optical signals, which considerably reduces the optical power received by the photodetectors. In this paper we propose a differential transmission of the modulated signals, which contributes to improve the transmission of the optical signal power on the receiver side. With this approach, it is possible to reduce the input laser power and increase the energy efficiency of the optical communication. The approach is generic and can be applied to SWSR-, MWSR-, SWMR- and MWMR-like architectures
FPGA Implementation of Embedded Cruise Control and Anti-Collision Radar
The ModEasy project seeks to develop techniques and software tools to aid in the development of reliable microprocessor based electronic (embedded) systems using advanced development and verification systems. The tools are to be evaluated in practical domains such as the automotive sector for reactive cruise control and anti-collision radar. We choose to define specific IPs using FPGA techniques to cover this application domain. This paper presents the implementation of such a complex and safety application on a single FPGA. The target system is composed of a reactive cruise control, a detection radar and the associated treatments
Thermal Aware Design Method for VCSEL-Based On-Chip Optical Interconnect
Optical Network-on-Chip (ONoC) is an emerging technology considered as one of
the key solutions for future generation on-chip interconnects. However, silicon
photonic devices in ONoC are highly sensitive to temperature variation, which
leads to a lower efficiency of Vertical-Cavity Surface-Emitting Lasers
(VCSELs), a resonant wavelength shift of Microring Resonators (MR), and results
in a lower Signal to Noise Ratio (SNR). In this paper, we propose a methodology
enabling thermal-aware design for optical interconnects relying on
CMOS-compatible VCSEL. Thermal simulations allow designing ONoC interfaces with
low gradient temperature and analytical models allow evaluating the SNR.Comment: IEEE International Conference on Design Automation and Test in Europe
(DATE 2015), Mar 2015, Grenoble, France. 201
A High Level Synthesis Flow Using Model Driven Engineering
Intensive Signal Processing (ISP) applications handle large amounts of data and are characterized by hierarchical and data parallel tasks, which manip- ulate multidimensional data arrays according to complex data dependencies. Performance requirements often preclude ISP applications from being im- plemented purely in software and instead call for using custom and efficient hardware accelerators. A hardware accelerator is an electronic design dedi- cated to the execution of a specific application. Its hardware architecture can be designed for a maximal parallelization of the algorithm needed to execute its application and for optimal execution support for regular and repetitive tasks. However, the complexity of hardware accelerators makes them difficult to manipulate at low abstraction levels (in a Hardware Description Language (HDL) for instance). The description of complex ISP applications is also error prone and tedious when using tools that constrain the number of dimensions of data arrays. High Level Synthesis (HLS) seeks to simplify the design of hardware accel- erators by describing applications at a high abstraction level and by generat- ing the corresponding low level implementation. Application specification is easier at a high abstraction level since hardware designers do not need to han- dle all low level implementation details. HLS thus aims to achieve algorithm- architecture matching by construction, through the automated synthesis of a hardware architecture for an application specified at a high level. The automatic generation of low level implementations drastically reduces non- recurring engineering costs and the time to market compared to hand-tuned implementations in HDL. For these reasons, HLS tools have been increasingly successful among the hardware designer community. This trend is followed by the continual integration of new capabilities and functionality in the tools. Therefore, successful HLS has to support rapidly evolving technologies and be maintainable in order to capitalize on efforts. We present some design challenges faced by HLS and how model-driven engineering can meet them
Energy and Performance Trade-off in Nanophotonic Interconnects using Coding Techniques
International audienceNanophotonic is an emerging technology considered as one of the key solutions for future generation on-chip interconnects. Indeed, this technology provides high bandwidth for data transfers and can be a very interesting alternative to bypass the bottleneck induced by classical NoC. However, their implementation in fully integrated 3D circuits remains uncertain due to the high power consumption of on-chip lasers. However, if a specific bit error rate is targeted, digital processing can be added in the electrical domain to reduce the laser power and keep the same communication reliability. This paper addresses this problem and proposes to transmit encoded data on the optical interconnect, which allows for a reduction of the laser power consumption, thus increasing nanophotonics interconnects energy efficiency. The results presented in this paper show that using simple Hamming coder and decoder permits to reduce the laser power by nearly 50% without loss in communication data rate and with a negligible hardware overhead
Gestion de la consommation d'un ONoC intégré dans un MPSoC
National audienceL'optique intégrée est une technologie très prometteuse qui permet d'envisager l'intégration de réseaux sur puce très per-formants. Toutefois, la consommation des composants optiques est critique et en particulier la consommation des sources laser intégrées est connue pour être importante. Dans ce contexte, l'implémentation d'un réseau optique sur puce nécessite une gestion précise des puissances d'émission des lasers. Dans ce contexte, les travaux que nous adressons concernent la modélisation des pertes subies par un signal optique circulant dans un guide d'ondes et l'insertion de codes correcteur d'erreurs pour parvenir à maintenir un taux d'erreur binaire ciblé. Cet article présente le principe de la stratégie que nous développons dans ce cadre
Gaspard2 UML profile documentation
This document describes the current UML profile of Gaspard2. This profile extends the UML semantics to allow the user to describe a SoC (System-on-Chip) in three steps: the application (behavior of the Soc), the hardware architecture, and the association of the application to the hardware architecture. The application is represented following a data flow model, but additional mechanisms permit the usage of control flow on those applications. In addition to those notions, the profile contains a package introducing factorization mechanisms to enable the compact description of massively parallel and repetitive systems
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